Efficient steady-state analysis based on matrix-free Krylov-subspace methods
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A high-level design and optimization tool for analog RF receiver front-ends
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Synthesis and layout for analog and mixed-signal ICs in the ACACIA system
Analog circuit design
Generalized constraint generation for analog circuit design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Simulation methods for RF integrated circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Analog Device-Level Layout Automation
Analog Device-Level Layout Automation
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
DAC '82 Proceedings of the 19th Design Automation Conference
An analysis of the behavior of a class of genetic adaptive systems.
An analysis of the behavior of a class of genetic adaptive systems.
Layout tools for analog ICs and mixed-signal SoCs: a survey
ISPD '00 Proceedings of the 2000 international symposium on Physical design
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High-frequency circuits are notoriously difficult to lay out because of the tight coupling between device-level placement and wiring. Given that successful electrical performance requires careful control of the lowest-level geometric features—wire bends, precise length, proximity, planarity, etc.—we suggest a new layout strategy for these circuits: early floorplanning at the device level. This paper develops a floorplanner for RF circuits based on a genetic algorithm (GA) that supports fully simultaneous placement and routing. The GA evolves slicing-style floorplans comprising devices and planned areas for wire meanders. Each floorplan candidate is fully routed with a gridless, detailed maze-router which can dynamically resize the floorplan as necessary. Experimental results demonstrate the ability of this approach to successfully optimize for wire planarity, realize multiple constraints on net lengths or phases, and achieve reasonable area in modest CPU times.