Synthesis tools for mixed-signal ICs: progress on frontend and backend strategies
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Device-level early floorplanning algorithms for RF circuits
ISPD '98 Proceedings of the 1998 international symposium on Physical design
CYCLONE: automated design and layout of RF LC-oscillators
Proceedings of the 37th Annual Design Automation Conference
Power estimation methods for analog circuits for architectural exploration of integrated systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACTIF: a high-level power estimation tool for analog continuous-time filters
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
CAD solutions and outstanding challenges for mixed-signal and RFIC design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Synthesis of analog and mixed-signal integrated electronic circuits
Formal engineering design synthesis
Classification of analog synthesis tools based on their architecture selection mechanisms
Integration, the VLSI Journal
A behavioral-based multi-agent optimization algorithm for system level radio design
Analog Integrated Circuits and Signal Processing
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This paper presents a high-level analysis and optimization tool for the design of analog RF receiver front-ends, which takes all design parameters and all aspects of performance degradation (noise, distortion, self-mixing...) into account. The simulations are performed in the spectral domain with a behavioral model library for the RF building blocks. The tool allows to explore alternative RF receiver topologies as well as to investigate design trade-offs within each topology. By having integrated the performance analysis routine within a simulated annealing optimization loop, the tool can also perform an optimal high-level synthesis of a given topology towards a specific application. It then determines the optimal specifications for the RF building blocks such that the required receiver signal quality is met while the overall power and/or area consumption is minimized.