Calculating the maximum, execution time of real-time programs
Real-Time Systems
A datapath synthesis system for the reconfigurable datapath architecture
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Program Improvement by Source-to-Source Transformation
Journal of the ACM (JACM)
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Digital Image Processing
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
The Power Test for Data Dependence
IEEE Transactions on Parallel and Distributed Systems
An Integrated Design Environment for Application Specific Integrated Processor
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Data-Procedural Languages for FPL-based Machines
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
XC6200 FastmapTM Processor Interface
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Configurable logic: a dynamically programmable cellular architecture and its vlsi implementation
Configurable logic: a dynamically programmable cellular architecture and its vlsi implementation
Synthesis of application specific instruction sets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 6th international workshop on Hardware/software codesign
A HW/SW partitioning algorithm for dynamically reconfigurable architectures
Proceedings of the conference on Design, automation and test in Europe
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Modifying Min-Cut for Hardware and Software Functional Partitioning
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Pipelining-based tradeoffs for hardware/software codesign of multimedia systems
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
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The partitioning of image processing algorithms with a novel hardware/software co-design framework (CoDe-X) is presented in this paper, where a new Xputer-architecture (parallel Map-oriented Machine) is used as universal accelerator based on a reconfigurable datapath hardware for speeding-up image processing applications. CoDe-X accepts C-programs and carries out both, the profiling-driven host/accelerator partitioning for performance optimization, and the resource-driven sequential/structural partitioning of the accelerator source code to optimize the utilization of its reconfigurable datapath resources.