A flexible architecture for image processing
Microprocessing and Microprogramming
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Optimally profiling and tracing programs
ACM Transactions on Programming Languages and Systems (TOPLAS)
Performance analysis of embedded software using implicit path enumeration
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A datapath synthesis system for the reconfigurable datapath architecture
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Design Automation for Embedded Systems
Program Improvement by Source-to-Source Transformation
Journal of the ACM (JACM)
Digital Image Processing
Computer
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
The Power Test for Data Dependence
IEEE Transactions on Parallel and Distributed Systems
A Partitioning Programming Environment for a Novel Parallel Architecture
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Data-Procedural Languages for FPL-based Machines
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Reconfigurable Processing With Field Programmable Gate Arrays
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators
HICSS '97 Proceedings of the 30th Hawaii International Conference on System Sciences: Advanced Technology Track - Volume 5
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The paper presents the performance analysis process within the parallelizing compilation environment CoDe-X for simultaneous programming of Xputer-based accelerators and their host. The paper introduces briefly its hardware/software co-design strategies at two levels of partitioning. CoDe-X performs both, at first level a profiling-driven host/accelerator partitioning for performance optimization, and at second level a resource-driven sequential/structural partitioning of the accelerator source code to optimize the utilization of its reconfigurable resources. The analysis of candidate (task) performances in CoDe-X has to be done for both, a procedural (sequential) programmable host processor, and the structural programmable data-driven accelerator processor. In complete application time estimation data-dependencies for parallel task execution (host/accelerators) are considered. To stress the significance of this application development methodology, the paper first gives an introduction to the target hardware platform.