Calculating the maximum, execution time of real-time programs
Real-Time Systems
Supercompilers for parallel and vector computers
Supercompilers for parallel and vector computers
A novel paradigm of parallel computation and its use to implement simple high performance hardware
CONPAR 90 Proceedings of the joint international conference on Vector and parallel processing
A datapath synthesis system for the reconfigurable datapath architecture
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Program Improvement by Source-to-Source Transformation
Journal of the ACM (JACM)
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Dependence Analysis for Supercomputing
Dependence Analysis for Supercomputing
An Empirical Study of Fortran Programs for Parallelizing Compilers
IEEE Transactions on Parallel and Distributed Systems
The Power Test for Data Dependence
IEEE Transactions on Parallel and Distributed Systems
Data-Procedural Languages for FPL-based Machines
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Two-Level Hardware/Software Partitioning Using CoDe-X
ECBS '96 Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems
Testing flow graph reducibility
Journal of Computer and System Sciences
Design of a high-throughput low-power IS95 Viterbi decoder
Proceedings of the 39th annual Design Automation Conference
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Design of a 20-Mb/s 256-state viterbi decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The paper presents a partitioning and parallelizing programming environment for a novel parallel architecture. This universal embedded accelerator is based on a reconfigurable datapath hardware. The partitioning and parallelizing programming environment accepts C programs and carries out both a profiling-driven host/accelerator partitioning for performance optimization in a first step, and in a second step a resource-driven sequential/structural partitioning of the accelerator source code to optimize the utilization of its reconfigurable resources.