Memory-CPU size optimization for embedded system designs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hierarchical test generation and design for testability of ASPPs and ASIPs
DAC '97 Proceedings of the 34th annual Design Automation Conference
Application of instruction analysis/synthesis tools to x86's functional unit allocation
Proceedings of the 11th international symposium on System synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Automatic application-specific instruction-set extensions under microarchitectural constraints
Proceedings of the 40th annual Design Automation Conference
Architectural Considerations for Application-Specific Counterflow Pipelines
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
High Level Synthesis from Sim-nML Processor Models
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Processor Acceleration Through Automated Instruction Set Customization
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications
IEEE Transactions on Computers
Automatic application-specific instruction-set extensions under microarchitectural constraints
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
International Journal of Parallel Programming - Special issue: Workshop on application specific processors (WASP)
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration
IEEE Transactions on Computers
Battery-aware instruction generation for embedded processors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Scalable subgraph mapping for acyclic computation accelerators
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Instruction set synthesis with efficient instruction encoding for configurable processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.04 |
In instruction set serves as the interface between hardware and software in a computer system. In an application specific environment, the system performance can be improved by designing an instruction set that matches the characteristics of hardware and the application. We present a systematic approach to generate application-specific instruction sets so that software applications can be efficiently mapped to a given pipelined micro-architecture. The approach synthesizes instruction sets from application benchmarks, given a machine model, an objective function, and a set of design constraints. In addition, assembly code is generated to show how the benchmarks can be compiled with the synthesized instruction set. The problem of designing instruction sets is formulated as a modified scheduling problem. A binary tuple is proposed to model the semantics of instructions and integrate the instruction formation process into the scheduling process. A simulated annealing scheme is used to solve for the schedules. Experiments have shown that the approach is capable of synthesizing powerful instructions for modern pipelined microprocessors, and running with reasonable time and a modest amount of memory for large applications