High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Specifying representations of machine instructions
ACM Transactions on Programming Languages and Systems (TOPLAS)
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
The system architect's workbench
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Advanced ASIC Chip Synthesis: Using Synopsys' Design Compiler and PrimeTime
Advanced ASIC Chip Synthesis: Using Synopsys' Design Compiler and PrimeTime
Hardware Synthesis from Term Rewriting Systems
VLSI '99 Proceedings of the IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration: Systems on a Chip
The mimola design system: Tools for the design of digital processors
DAC '84 Proceedings of the 21st Design Automation Conference
Processor Models for Retargetable Tools
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
Retargetable Functional Simulator Using High Level Processor Models
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Matching system and component behaviour in MIMOLA synthesis tools
EURO-DAC '90 Proceedings of the conference on European design automation
Synthesis of application specific instruction sets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Automatic generation of memory interfaces
SOC'09 Proceedings of the 11th international conference on System-on-chip
Generating interlocked instruction pipelines from specifications of instruction sets
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Automatic Generation of Memory Interfaces for ASIPs
International Journal of Embedded and Real-Time Communication Systems
Resource-constrained high-level datapath optimization in ASIP design
Proceedings of the Conference on Design, Automation and Test in Europe
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The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML [1] is a specification language to model processors forsuch designs. Several software generation tools have beendeveloped that take ISA specifications in Sim-nML as input.In this paper we present a tool Sim-HS that implementshigh level behavioral and structural synthesis of processorsfrom their ISA specifications in Sim-nML. Behavioral Sim-HS transforms Sim-nML specifications of a processor tothe corresponding behavioral Verilog model that is suitablefor fast functional simulation. Structural Sim-HS generatesstructural synthesizable Verilo processor model from itsSim-nML specifications.