Allocation algorithms based on path analysis
Integration, the VLSI Journal - Special issue on high-level synthesis
False loops through resource sharing
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Quadratic zero-one programming based synthesis of application specific data paths
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
Resource sharing in hierarchical synthesis
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Behavioral network graph: unifying the domains of high-level and logic synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Architecture Exploration for Embedded Processors with Lisa
Architecture Exploration for Embedded Processors with Lisa
Layout-driven resource sharing in high-level synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A method of automatic data path synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
Processor Models for Retargetable Tools
RSP '00 Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000)
High Level Synthesis from Sim-nML Processor Models
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Synthesis-driven Exploration of Pipelined Embedded Processors
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs
Proceedings of the 41st annual Design Automation Conference
Optimization Techniques for ADL-Driven RTL Processor Synthesis
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Automatic application specific floating-point unit generation
Proceedings of the conference on Design, automation and test in Europe
Rapid application specific floating-point unit generation with bit-alignment
Proceedings of the 45th annual Design Automation Conference
Automatic architecture refinement techniques for customizing processing elements
Proceedings of the 45th annual Design Automation Conference
Processor Description Languages
Processor Description Languages
Custom floating-point unit generation for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Resource-constrained high-level datapath optimization in ASIP design
Proceedings of the Conference on Design, Automation and Test in Europe
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Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Processors (ASIPs), benefiting from automatically generated software tool suite and RTL implementation. The increase of abstraction level and automated implementation traditionally comes at the cost of low area, delay or power efficiency. The standard synthesis flow starting at RTL abstraction fails to compensate for this loss of performance. Thus, high level optimizations during RTL synthesis from ADLs are obligatory. Currently, ADL-based optimization schemes do not perform resource sharing. In this paper, we present an iterative algorithm for performing resource sharing on the basis of global data flow graph matching criteria. This ADL-based resource sharing optimization is performed over a RISC and a VLIW architecture and two industrial embedded processors. The results indicate a significant improvement in overall performance. A comparative study with manually written RTL code is presented, too.