3D scheduling: high-level synthesis with floorplanning
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Simultaneous functional-unit binding and floorplanning
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A grid-based approach for connectivity binding with geometric costs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Integrating floorplanning in data-transfer based high-level synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Approximating the throughput of multiple machines under real-time scheduling
STOC '99 Proceedings of the thirty-first annual ACM symposium on Theory of computing
Behavior-to-placed RTL synthesis with performance-driven placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Architecture and synthesis for multi-cycle communication
Proceedings of the 2003 international symposium on Physical design
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Automatic application specific floating-point unit generation
Proceedings of the conference on Design, automation and test in Europe
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Rapid application specific floating-point unit generation with bit-alignment
Proceedings of the 45th annual Design Automation Conference
Custom floating-point unit generation for embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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In deep submicron (DSM) technology, the interconnects are equally as or more important than the logic gates. In particular, to achieve timing closure in DSM technology, it is very necessary and critical to consider the interconnect delay at an early stage of the synthesis process. It has been known that resource sharing in high-level synthesis is one of the major synthesis tasks which greatly affect the final synthesis/layout results. In this paper, we propose a new layout-driven resource sharing approach to overcome some of the limitations of the previous works in which the effects of layout on the synthesis have never been taken into account or considered in local and limited ways, or whose computation time is excessively large. The proposed approach consists of two steps: (Step 1) We relax the integrated resource sharing and placement into an efficient linear programming (LP) formulation based on the concept of discretizing placement space; (Step 2) We derive a feasible solution from the solution obtained in Step 1. Then, we employ an iterative mechanism based on the two steps to tightly integrate resource sharing and placement tasks so that the slack time violation due to interconnect delay (determined by placement) as well as logic delay (determined by resource sharing) should be minimized. From experiments using a set of benchmark designs, it is shown that the approach is effective, and efficient, completely removing the slack time violation produced by conventional methods.