Behavior-to-placed RTL synthesis with performance-driven placement

Authors:
Daehong Kim;Jinyong Jung;Sunghyun Lee;Jinhwan Jeon;Kiyoung Choi
Affiliations:
Seoul National University, Seoul, Korea;Seoul National University, Seoul, Korea;Seoul National University, Seoul, Korea;GCT Research, Inc., Seoul, Korea;Seoul National University, Seoul, Korea
Venue:
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Year:
2001

Citing 12
Cited 18

Principles of CMOS VLSI design: a systems perspective

Principles of CMOS VLSI design: a systems perspective
Performance-driven constructive placement

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
3D scheduling: high-level synthesis with floorplanning

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design

High-level synthesis: introduction to chip and system design
System clock estimation based on clock slack minimization

EURO-DAC '92 Proceedings of the conference on European design automation
Simultaneous functional-unit binding and floorplanning

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Getting to the bottom of deep submicron

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Integrating floorplanning in data-transfer based high-level synthesis

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Figures of merit to characterize the importance of on-chip inductance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-level synthesis under multi-cycle interconnect delay

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Synthesis and Optimization of Digital Circuits

Synthesis and Optimization of Digital Circuits
Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis

VLSID '98 Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing

Architecture and synthesis for multi-cycle communication

Proceedings of the 2003 international symposium on Physical design
Layout-driven resource sharing in high-level synthesis

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Architecture and synthesis for multi-cycle on-chip communication

Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A cycle-accurate compilation algorithm for custom pipelined datapaths

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Resource Sharing Combined with Layout Effects in High-Level Synthesis

Journal of VLSI Signal Processing Systems
Platform-based resource binding using a distributed register-file microarchitecture

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Interconnect and communication synthesis for distributed register-file microarchitecture

Proceedings of the 44th annual Design Automation Conference
FPGA Design Automation: A Survey

Foundations and Trends in Electronic Design Automation
Compatibility path based binding algorithm for interconnect reduction in high level synthesis

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A multicycle communication architecture and synthesis flow for global interconnect resource sharing

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power optimization with power islands synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level synthesis with distributed controller for fast timing closure

Proceedings of the International Conference on Computer-Aided Design
3DHLS: incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Critical-path-aware high-level synthesis with distributed controller for fast timing closure

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Quantified Score

Hi-index	0.00

Visualization

Abstract

Interconnect delay should be considered together with computation delay during architectural synthesis in order to achieve timing closure in deep submicrometer technology. In this paper, we propose an architectural synthesis technique for distributed-register architecture, which separates interconnect delay for data transfer from component delay for computation. The technique incorporates performance-driven placement into the architectural synthesis to minimize performance overhead due to interconnect delay. Experimental results show that our methodology achieves performance improvement of up to 60% and 22% on the average.