Integrated scheduling and binding: a synthesis approach for design space exploration
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Synthesis of optimal clocking schemes
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Algorithms for High-Level Synthesis
IEEE Design & Test
An exact methodology for scheduling in a 3D design space
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Clock optimization for high-performance pipelined design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Performance analysis of a system of communicating processes
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Performance-driven scheduling with bit-level chaining
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Efficient optimal design space characterization methodologies
ACM Transactions on Design Automation of Electronic Systems (TODAES)
False path exclusion in delay analysis of RTL structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavior-to-placed RTL synthesis with performance-driven placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
System Specification with the SpecCharts Language
IEEE Design & Test
A Co-Design Methodology Based on Formal Specification and High-level Estimation
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Optimal Clock Period for Synthesized Data Paths
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Heuristic for Clock Selection in High-Level Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Toward a Practical Methodology for Completely Characterizing the Optimal Design Space
ISSS '96 Proceedings of the 9th international symposium on System synthesis
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
HLS-l: a high-level synthesis framework for latch-based architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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