ACM Computing Surveys (CSUR)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Principles of Compiler Design (Addison-Wesley series in computer science and information processing)
Circuit implementation of high-speed pipeline systems
AFIPS '65 (Fall, part I) Proceedings of the November 30--December 1, 1965, fall joint computer conference, part I
Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems
IEEE Transactions on Computers
System clock estimation based on clock slack minimization
EURO-DAC '92 Proceedings of the conference on European design automation
An exact methodology for scheduling in a 3D design space
ISSS '95 Proceedings of the 8th international symposium on System synthesis
An optimal clock period selection method based on slack minimization criteria
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock optimization for high-performance pipelined design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Principles of the SYCO compiler
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
| Hi-index | 0.00 |
Clocking scheme synthesis includes the partitioning of functions into time steps, the number of clock phases, the length of each phase, (i.e. how to pipeline) and the assignment of functions to clock phases; each of these choices affects performance. Some important problems of clocking scheme synthesis are examined. Two efficient and powerful algorithms which synthesize near optimal clocking schemes have been programmed. These algorithms are applied to synthesis and/or performance evaluation of a design in progress. Optimizing the speed of a previously designed system is also considered.