The Silc silicon compiler: language and features
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Synthesis of optimal clocking schemes
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A new synthesis for the MIMOLA software system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Sehwa: a program for synthesis of pipelines
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Integrated scheduling and binding: a synthesis approach for design space exploration
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A technology-adaptive allocation of functional units and connections
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Constraint sensitive scheduling in RASP
ACM SIGDA Newsletter
Optimum and heuristic data path scheduling under resource constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Memory, control and communications synthesis for scheduled algorithms
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Fast and near optimal scheduling in automatic data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Redundant operator creation: a scheduling optimization technique
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
SYNTEST: an environment for system-level design for test
EURO-DAC '92 Proceedings of the conference on European design automation
An approach for redesigning in data path synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
MIST—a design aid for programmable pipelined processors
DAC '94 Proceedings of the 31st annual Design Automation Conference
Interconnection synthesis with geometric constraints
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
The system architect's workbench
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
High-level synthesis: current status and future directions
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Efficiency improvements for force-directed scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
High-quality operation binding for clustered VLIW datapaths
Proceedings of the 38th annual Design Automation Conference
Cluster assignment for high-performance embedded VLIW processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
From Behavior to Structure: High-Level Synthesis
IEEE Design & Test
Design Synthesis and Silicon Compilation
IEEE Design & Test
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
Estimating the Complexity of Synthesized Designs from FSM Specifications
IEEE Design & Test
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems
IEEE Design & Test
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
Exact scheduling strategies based on bipartite graph matching
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Towards a global solution to high level synthesis problems
EURO-DAC '90 Proceedings of the conference on European design automation
High level synthesis: a data path partitioning method dedicated to speed enhancement
EURO-DAC '91 Proceedings of the conference on European design automation
Area and performance optimizations in path-based scheduling
EURO-DAC '91 Proceedings of the conference on European design automation
CASCH: a scheduling algorithm for "high level"-synthesis
EURO-DAC '91 Proceedings of the conference on European design automation
Improved force-directed scheduling
EURO-DAC '91 Proceedings of the conference on European design automation
Integrated temporal and spatial scheduling for extended operand clustered VLIW processors
Proceedings of the 1st conference on Computing frontiers
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A scheduling algorithm for optimization and early planning in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Defining an Enhanced RTL Semantics
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Instruction scheduling using MAX-MIN ant system optimization
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Design space exploration using time and resource duality with the ant colony optimization
Proceedings of the 43rd annual Design Automation Conference
Resource-constrained loop scheduling in high-level synthesis
Proceedings of the 43rd annual Southeast regional conference - Volume 2
A spatial path scheduling algorithm for EDGE architectures
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Area-efficient arithmetic expression evaluation using deeply pipelined floating-point cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Finding the best compromise in compiling compound loops to Verilog
Journal of Systems Architecture: the EUROMICRO Journal
Dimensioning heterogeneous MPSoCs via parallelism analysis
Proceedings of the Conference on Design, Automation and Test in Europe
An energy and power-aware approach to high-level synthesis of asynchronous systems
Proceedings of the International Conference on Computer-Aided Design
DESCOMP: a new design space exploration approach
ARCS'05 Proceedings of the 18th international conference on Architecture of Computing Systems conference on Systems Aspects in Organic and Pervasive Computing
Multi-pumping for resource reduction in FPGA high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting area/delay tradeoffs in high-level synthesis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Multi-token resource sharing for pipelined asynchronous systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
The benefits of using variable-length pipelined operations in high-level synthesis
ACM Transactions on Embedded Computing Systems (TECS)
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The HAL system performs data path synthesis using a new scheduling algorithm that is part of an interdependent scheduling and allocation scheme. This scheme uses an estimate of the hardware allocation to guide and optimize the scheduling subtask. The allocation information includes the number, type, speed and cost of hardware modules as well as the associated multiplexer and interconnect costs.The iterative force-directed scheduling algorithm attempts to balance the distribution of operations that make use of the same hardware resources:Every feasible control step assignment is evaluated at each iteration, for all operations.The associated side-effects on all the predecessor and successor operations are taken into account.All the decisions are global.The algorithm has O(n8 complexity.We review and compare existing scheduling techniques. Moderate and difficult examples are used to illustrate the effectiveness of the approach.