Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
HYPER-LP: a system for power minimization using architectural transformations
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Distributed design-space exploration for high-level synthesis systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Low-power architectural design methodologies
Low-power architectural design methodologies
Splicer: a heuristic approach to connectivity binding
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench
IEEE Design & Test
SYCLOP: Synthesis of CMOS Logic for Low Power Applications
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Facet: A procedure for the automated synthesis of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hierarchical behavioral partitioning for multicomponent synthesis
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Simulation based architectural power estimation for PLA-based controllers
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Tools and methodologies for low power design
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Efficient switching activity computation during high-level synthesis of control-dominated designs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
IMPACT: a high-level synthesis system for low power control-flow intensive circuits
Proceedings of the conference on Design, automation and test in Europe
Power optimization and management in embedded systems
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A comprehensive high-level synthesis system for control-flow intensive behaviors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Energy Efficient Scheduling for Datapath Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A precise high-level power consumption model for embedded systems software
EURASIP Journal on Embedded Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a profile-driven approach to behavior level synthesis. In this approach, event activities related to various operations and carriers in the behavioral specification are measured by simulating the description using user-supplied profiling stimuli. These event activities are then used during the synthesis process to estimate the switching activity in the design being synthesized. Overall switching activity estimation is based on modulating the average intrinsic switching activities of the synthesis library modules using the event activities. This estimate is used to select a module set and a schedule which, besides meeting the area and clock-speed constraints, would minimize the switching activity in the design. Experimental results for a number of examples show that the switching activity estimated during synthesis deviates by less than 10% on the average from the actual switching activity measured after completing synthesis.The same profile-driven approach is applied to estimate the total amount of capacitance that would switch in the design when the given stimuli is applied. Again, experimental results show that, on the average, the estimated switched capacitance deviates from the actual measured value by about 12%.