Energy Efficient Scheduling for Datapath Synthesis

  • Authors:
  • Saraju P. Mohanty;N. Ranganathan

  • Affiliations:
  • -;-

  • Venue:
  • VLSID '03 Proceedings of the 16th International Conference on VLSI Design
  • Year:
  • 2003

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Abstract

In this paper, we describe two new algorithms for data-pathscheduling which aim at energy reduction while maintainingperformance. The proposed algorithms, time constrainedand resource constrained, utilize the concepts ofmultiple supply voltage and dynamic clocking for energyminimization. In dynamic clocking, the functional unitscan be operated at different frequencies depending on thecomputations occurring within the datapath during a givenclock cycle. The strategy is to schedule high energy units,such as the multipliers at lower frequencies such that theycan be operated at lower voltages to reduce energy consumptionand the low energy units, such as adders at higherfrequencies, to compensate for speed. The algorithms havebeen applied to various high level synthesis benchmark circuitsunder different time and resource constraints. The experimentalresults show that for the time constrained algorithm,energy savings in the range of 33 - 75% are obtained.Similarly, for resource constrained algorithm, under variousresource constraints using two supply voltage levels(5.0V,3.3V ), energy savings in the range of 24 - 53% canbe obtained.