Scheduling techniques for variable voltage low power designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Power-aware modulo scheduling for high-performance VLIW processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Transient power management through high level synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Optimizing Power in ASIC Behavioral Synthesis
IEEE Design & Test
Power-Driven Challenges in Nanometer Design
IEEE Design & Test
High Level Synthesis for Peak Power Minimization Using ILP
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Energy Efficient Scheduling for Datapath Synthesis
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Peak Power Minimization Through Datapath Scheduling
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Telescopic units: a new paradigm for performance optimization of VLSI designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven high-level synthesis with bit-level chaining and clock selection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A game theoretic approach for power optimization during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using deep submicron and nanometer technology, the peak power, peak power differential, average power and total energy are equally critical design constraints. In this work, we propose datapath scheduling algorithms for simultaneous minimization of peak and average power while maintaining performance by use of dynamic frequency clocking and multiple supply voltages. The algorithms use integer linear programming based models. The dynamic frequency clocking methodology is more useful for data intensive signal processing applications. The effectiveness of our scheduling technique is measured by estimating the peak power consumption, the average power consumption and the power delay product of the datapath circuit. Furthermore, the proposed scheduling scheme is compared with combined multiple supply voltages and multicycling scheme. Experimental results show that combined multiple supply voltages (3.3V,2.4V) and dynamic frequency clocking scheme achieves significant reductions in peak power (72% on the average), average power (71% on the average) and power delay product (54% on the average).