Simultaneous peak and average power minimization during datapath scheduling for DSP processors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Highly flexible multi-mode system synthesis
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Arrival time aware scheduling to minimize clock cycle length
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ILP models for simultaneous energy and transient power minimization during behavioral synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The impact of loop unrolling on controller delay in high level synthesis
Proceedings of the conference on Design, automation and test in Europe
Area optimization of multi-cycle operators in high-level synthesis
Proceedings of the conference on Design, automation and test in Europe
EURASIP Journal on Applied Signal Processing
Performance-driven scheduling of behavioural specifications
Integration, the VLSI Journal
Frequent-pattern-guided multilevel decomposition of behavioral specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
HLS-l: a high-level synthesis framework for latch-based architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using speculative functional units in high level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
HLS-l: high-level synthesis of high performance latch-based circuits
Proceedings of the Conference on Design, Automation and Test in Europe
A clock control strategy for peak power and RMS current reduction using path clustering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a new scheme for scheduling and control synthesis in high-level circuit design. The scheduling algorithm tries to maximize the performance of a design under resource constraints by maximizing the utilization of resources and minimizing clock slack. It exploits the technique of bit-level chaining (BLC) to target high-speed design. It also exploits noninteger multicycling and chaining, which allows multiple cycle execution of a set of chained operations and even sharing of chained functional units to obtain further performance at the cost of a small increase in the complexity of the control unit. Experimental results on several datapath-intensive designs show significant improvement in throughput over the conventional scheduling algorithms