High-level synthesis of fault-secure microarchitectures
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis of application specific programmable processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Area optimization of multi-functional processing units
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Computer and Robot Vision
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A new approach to pipeline optimisation
EURO-DAC '90 Proceedings of the conference on European design automation
Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area Overhead
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Flexibility measurement of domain-specific reconfigurable hardware
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance-driven high-level synthesis with bit-level chaining and clock selection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Construction of dual mode components for reconfiguration aware high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Design of multi-mode application-specific cores based on high-level synthesis
Integration, the VLSI Journal
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Multimode systems have emerged as an area- and power-efficient platform for implementing multiple timewise mutually exclusive digital signal processing (DSP) applications in a single hardware space. This paper presents a design methodology for integrating flexible components and controllers into primarily fixed logic multimode DSP systems, thereby increasing their overall efficiency and implementation capabilities. The components are built using a technique called small-scale reconfigurability (SSR) that provides the necessary flexibility for both intermode and intramode reconfigurabilities, without the penalties associated with general-purpose reconfigurable logic. Using this methodology, area and power consumption are reduced beyond what is provided by current multimode systems, without sacrificing performance. The results show an average of 7% reduction in datapath component area, 26% reduction in register area, 36% reduction in interconnect MUX cost, and 68% reduction in the number of controller signals, with an average 38% increase in component utilization for a set of benchmark 32-bit DSP applications.