Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Transformation-based high-level synthesis of fault-tolerant ASICs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Fault-secure algorithms for multiple-processor systems
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Introspection: a low overhead binding technique during self-diagnosing microarchitecture synthesis
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Concurrent error detection at architectural level
Proceedings of the 11th international symposium on System synthesis
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis
IEEE Transactions on Computers
Behavioral synthesis of fault secure controller/datapaths using aliasing probability analysis
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Highly flexible multi-mode system synthesis
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
EURASIP Journal on Applied Signal Processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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