High-level synthesis of fault-secure microarchitectures
DAC '93 Proceedings of the 30th international Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
Semi-Concurrent Error Detection in Data Paths
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
A unified lower bound estimation technique for high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RT level reliability enhancement by constructing dynamic TMRS
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Agent-based error prevention algorithms
Expert Systems with Applications: An International Journal
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