Computer arithmetic algorithms
Computer arithmetic algorithms
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Fault-secure shifter design: results and implementations
EDTC '97 Proceedings of the 1997 European conference on Design and Test
On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Concurrent error detection at architectural level
Proceedings of the 11th international symposium on System synthesis
A CAD framework for generating self-checking multipliers based on residue codes
DATE '99 Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fault Analysis for Networks with Concurrent Error Detection
IEEE Design & Test
Fault-Secure Parity Prediction Booth Multipliers
IEEE Design & Test
Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Parameterized VHDL Library for On-Line Testing
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Fault Detection Architectures for Field Multiplication Using Polynomial Bases
IEEE Transactions on Computers
Ultra low-cost defect protection for microprocessor pipelines
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
A low-cost concurrent error detection technique for processor control logic
Proceedings of the conference on Design, automation and test in Europe
Datapath error detection with no detection latency for high-performance microprocessors
WSEAS Transactions on Computers
Architecture Design for Soft Errors
Architecture Design for Soft Errors
New Self-Checking Booth Multipliers
International Journal of Applied Mathematics and Computer Science - Selected Problems of Computer Science and Control
On-line error detection and fast recover techniques for dependable embedded processors
On-line error detection and fast recover techniques for dependable embedded processors
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Although parity prediction arithmetic operators are compatible with systems checked by parity codes, they are not secure against single faults. The authors determine the necessary conditions for fault secureness and derive designs embodying these conditions