Efficient Exponentiation of a Primitive Root in GF(2m)
IEEE Transactions on Computers
On-Line Error Detection for Bit-Serial Multipliers in GF(2m)
Journal of Electronic Testing: Theory and Applications
Fast Arithmetic for Public-Key Algorithms in Galois Fields with Composite Exponents
IEEE Transactions on Computers
Mastrovito Multiplier for General Irreducible Polynomials
IEEE Transactions on Computers
IEEE Transactions on Computers
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis
IEEE Transactions on Computers
Error Detection in Polynomial Basis Multipliers over Binary Extension Fields
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
IEEE Transactions on Computers
Parallel Multipliers Based on Special Irreducible Pentanomials
IEEE Transactions on Computers
Elliptic Curve Cryptosystems in the Presence of Permanent and Transient Faults
Designs, Codes and Cryptography
Low Cost Concurrent Error Detection for the Advanced Encryption Standard
ITC '04 Proceedings of the International Test Conference on International Test Conference
On concurrent detection of errors in polynomial basis multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2m)
Integration, the VLSI Journal
Journal of Signal Processing Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Concurrent error detection architectures for field multiplication using gaussian normal basis
ISPEC'10 Proceedings of the 6th international conference on Information Security Practice and Experience
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In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. In this paper, we propose new architectures to detect erroneous outputs caused by certain types of faults in bit-parallel and bit-serial polynomial basis multipliers over finite fields of characteristic two. In particular, parity prediction schemes are developed for detecting errors due to single and certain multiple stuck-at faults. Although the issue of detecting soft errors in registers is not considered, the proposed schemes have the advantage that they can be used with any irreducible binary polynomial chosen to define the finite field.