Proceedings of the conference on Design, automation and test in Europe: Proceedings
Simple Error Detection Methods for Hardware Implementation of Advanced Encryption Standard
IEEE Transactions on Computers
Fault Detection Architectures for Field Multiplication Using Polynomial Bases
IEEE Transactions on Computers
On concurrent detection of errors in polynomial basis multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable hardware for high-security/high-performance embedded systems: the SAFES perspective
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Differential fault analysis on the ARIA algorithm
Information Sciences: an International Journal
Error detection and error correction procedures for the advanced encryption standard
Designs, Codes and Cryptography
High-Performance Concurrent Error Detection Scheme for AES Hardware
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
A compact ASIC implementation of the advanced encryption standard with concurrent error detection
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
A compact AES core with on-line error-detection for FPGA applications with modest hardware resources
Microprocessors & Microsystems
A Fault Detection Scheme for the FPGA Implementation of SHA-1 and SHA-512 Round Computations
Journal of Electronic Testing: Theory and Applications
A comparative cost/security analysis of fault attack countermeasures
FDTC'06 Proceedings of the Third international conference on Fault Diagnosis and Tolerance in Cryptography
Invariance-based concurrent error detection for advanced encryption standard
Proceedings of the 49th Annual Design Automation Conference
Fault detection of the macguffin cipher against differential fault attack
INTRUST'11 Proceedings of the Third international conference on Trusted Systems
Error detecting AES using polynomial residue number systems
Microprocessors & Microsystems
A fault-resistant implementation of AES using differential bytes between input and output
The Journal of Supercomputing
Hi-index | 0.01 |
We present a new low-cost concurrent checking method for the Advanced Encryption Standard (AES) encryption algorithm. In this method, the parity of the 128-bit input is determined and modified step-by-step into the parity of the 128-bit output according to the processing steps of the AES encryption. For the parity-preserving AES steps Shift-Rows and Mix-Column no parity modifications are necessary. The modified parity is compared in any round with the actual parity of the outputs of the round. To obtain the hardware costs we implemented this method on a Xilinx Virtex 1000 FPGA. For this implementation, the hardware overhead is about 8% and the additional time delay is about 5%. The method detects technical faults and deliberately injected faults during normal operation.