Differential Fault Analysis of Secret Key Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
A Highly Regular and Scalable AES Hardware Architecture
IEEE Transactions on Computers
IEEE Transactions on Computers
Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Low Cost Concurrent Error Detection for the Advanced Encryption Standard
ITC '04 Proceedings of the International Test Conference on International Test Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Error detection and error correction procedures for the advanced encryption standard
Designs, Codes and Cryptography
High-Performance Concurrent Error Detection Scheme for AES Hardware
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
A compact ASIC implementation of the advanced encryption standard with concurrent error detection
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications
Transactions on Data Privacy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A compact AES core with on-line error-detection for FPGA applications with modest hardware resources
Microprocessors & Microsystems
A Fault Detection Scheme for the FPGA Implementation of SHA-1 and SHA-512 Round Computations
Journal of Electronic Testing: Theory and Applications
A fault-resistant implementation of AES using differential bytes between input and output
The Journal of Supercomputing
| Hi-index | 14.98 |
In order to prevent the Advanced Encryption Standard (AES) from suffering from differential fault attacks, the technique of error detection can be adopted to detect the errors during encryption or decryption and then to provide the information for taking further action, such as interrupting the AES process or redoing the process. Because errors occur within a function, it is not easy to predict the output. Therefore, general error control codes are not suited for AES operations. In this work, several error-detection schemes have been proposed. These schemes are based on the (n+1,n) cyclic redundancy check (CRC) over GF(2^8), where n\in \{4,8,16\}. Because of the good algebraic properties of AES, specifically the MixColumns operation, these error detection schemes are suitable for AES and efficient for the hardware implementation; they may be designed using round-level, operation-level, or algorithm-level detection. The proposed schemes have high fault coverage. In addition, the schemes proposed are scalable and symmetrical. The scalability makes these schemes suitable for an AES circuit implemented in 8-bit, 32-bit, or 128-bit architecture. Symmetry also benefits the implementation of the proposed schemes to achieve that the encryption process and the decryption process can share the same error detection hardware. These schemes are also suitable for encryption-only or decryption-only cases. Error detection for the key schedule in AES is also proposed and is based on the derived results in the data procedure of AES.