Methods for encrypting and decrypting MPEG video data efficiently
MULTIMEDIA '96 Proceedings of the fourth ACM international conference on Multimedia
Multimedia Systems
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Architectures and VLSI Implementations of the AES-Proposal Rijndael
IEEE Transactions on Computers
A Highly Regular and Scalable AES Hardware Architecture
IEEE Transactions on Computers
AES Algorithm Implementation-An efficient approach for Sequential and Pipeline Architectures
ENC '03 Proceedings of the 4th Mexican International Conference on Computer Science
Power-Analysis Attack on an ASIC AES implementation
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
Impossible differential cryptanalysis of 7-round advanced encryption standard (AES)
Information Processing Letters - Devoted to the rapid publication of short contributions to information processing
A configurable AES processor for enhanced security
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Compact Piplined Hardware Implementation of the AES-128 Cipher
ITNG '06 Proceedings of the Third International Conference on Information Technology: New Generations
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
IEEE Transactions on Computers
Simple Error Detection Methods for Hardware Implementation of Advanced Encryption Standard
IEEE Transactions on Computers
Efficient frequency domain selective scrambling of digital video
IEEE Transactions on Multimedia
A high-throughput low-cost AES processor
IEEE Communications Magazine
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For real-time applications, there are several factors (time, cost, power) that are moving security considerations from a function centric perspective into a system architecture (hardware/software) design issue. Advanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address security issues. The AES algorithm specifies three key sizes: 128, 192 and 256 bits offering different levels of security. To deal with the amount of application and intensive computation given by security mechanisms, we define and develop a QoSS (Quality of Security Service) model for reconfigurable AES processor. QoSS has been designed and implemented to achieve a flexible trade-off between overheads caused by security services and system performance. The proposed architecture can provide up to 12 AES block cipher schemes within a reasonable hardware cost. We envisage a security vector in a fully functional QoSS request to include levels of service for the range of security service and mechanisms. Our unified hardware can run both the original AES algorithm and the extended AES algorithm (QoSS-AES). A novel on-the-fly AES encryption/ decryption design is also proposed for 128-, 192-, and 256-bit keys. The performance of the proposed processor has been analyzed in an MPEG4 video compression standard. The results revealed that the QoSS-AES processor is well suited to provide high security communication with low latencies. In our implementation based on Xilinx Virtex FPGAs, speed/area/power results from these processors are analyzed and shown to compare favorably with other well known FPGA based implementations.