An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks
IEEE Transactions on Dependable and Secure Computing
Power and electromagnetic analysis: improved model, consequences and comparisons
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
Proceedings of the 44th annual Design Automation Conference
RIJID: random code injection to mask power analysis based side channel attacks
Proceedings of the 44th annual Design Automation Conference
Computers and Electrical Engineering
A novel AES cryptographic core highly resistant to differential power analysis attacks
Proceedings of the 21st annual symposium on Integrated circuits and system design
Multiple-Differential Side-Channel Collision Attacks on AES
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Demonstrable differential power analysis attacks on real-world FPGA-based embedded systems
Integrated Computer-Aided Engineering
Side channel analysis of AVR XMEGA crypto engine
WESS '09 Proceedings of the 4th Workshop on Embedded Systems Security
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC
Electronic Notes in Theoretical Computer Science (ENTCS)
Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications
Transactions on Data Privacy
Combinatorial logic circuitry as means to protect low cost devices against side channel attacks
WISTP'07 Proceedings of the 1st IFIP TC6 /WG8.8 /WG11.2 international conference on Information security theory and practices: smart cards, mobile and ubiquitous computing systems
Design of a differential power analysis resistant masked AES S-box
INDOCRYPT'07 Proceedings of the cryptology 8th international conference on Progress in cryptology
Improving first order differential power attacks through digital signal processing
Proceedings of the 3rd international conference on Security of information and networks
Correlation power analysis based on switching glitch model
WISA'10 Proceedings of the 11th international conference on Information security applications
An area-efficient universal cryptography processor for smart cards
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Provably secure masking of AES
SAC'04 Proceedings of the 11th international conference on Selected Areas in Cryptography
Differential power analysis on block cipher ARIA
HPCC'05 Proceedings of the First international conference on High Performance Computing and Communications
A tutorial on physical security and side-channel attacks
Foundations of Security Analysis and Design III
Reverse engineering of embedded software using syntactic pattern recognition
OTM'06 Proceedings of the 2006 international conference on On the Move to Meaningful Internet Systems: AWeSOMe, CAMS, COMINF, IS, KSinBIT, MIOS-CIAO, MONET - Volume Part I
Successfully attacking masked AES hardware implementations
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Improved higher-order side-channel attacks with FPGA experiments
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Side-Channel leakage across borders
CARDIS'10 Proceedings of the 9th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Application
Randomized Instruction Injection to Counter Power Analysis Attacks
ACM Transactions on Embedded Computing Systems (TECS)
The schedulability of AES as a countermeasure against side channel attacks
SPACE'12 Proceedings of the Second international conference on Security, Privacy, and Applied Cryptography Engineering
Applying remote side-channel analysis attacks on a security-enabled NFC tag
CT-RSA'13 Proceedings of the 13th international conference on Topics in Cryptology
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The AES (Advanced Encryption Standard) is a new blockcipher standard published by the US government in November2001. As a consequence, there is a growing interestin efficient implementations of the AES. For many applications,these implementations need to be resistant againstside channel attacks, that is, it should not be too easy toextract secret information from physical measurements onthe device. This article presents the first results on the feasibilityof power analysis attack against an AES hardwareimplementation. Our attack is targeted against an ASIC implementationof the AES developed by the ETH Zurich. Weshow how to build a reliable measurement setup and how toimprove the correlation coefficients, i.e., the signal to noiseratio for our measurements. Our approach is also the firststep to link a behavior HDL simulator generated simulatedpower measurements to real power measurements.