Design of a differential power analysis resistant masked AES S-box

Authors:
Kundan Kumar;Debdeep Mukhopadhyay;Dipanwita RoyChowdhury
Affiliations:
Department of Computer Science and Engg., Indian Institute of Technology, Kharagpur, India;Department of Computer Science and Engg., Indian Institute of Technology, Madras, India;Department of Computer Science and Engg., Indian Institute of Technology, Kharagpur, India
Venue:
INDOCRYPT'07 Proceedings of the cryptology 8th international conference on Progress in cryptology
Year:
2007

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Abstract

Gate level masking is one of the most popular countermeasures against Differential Power Attack (DPA). The present paper proposes a masking technique for AND gates, which are then used to build a balanced and masked multiplier in GF(2n). The circuits are shown to be computationally secure and have no glitches which are dependent on unmasked data. Finally, the masked multiplier in GF(24) is used to implement a masked AES S-Box in GF(24)2. Power measurements are taken to support the claim of random power consumption.