Smart Card Security and Applications, Second Edition
Smart Card Security and Applications, Second Edition
Examining Smart-Card Security under the Threat of Power Analysis Attacks
IEEE Transactions on Computers
ACISP '01 Proceedings of the 6th Australasian Conference on Information Security and Privacy
Power-Analysis Attack on an ASIC AES implementation
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
Investigations of power analysis attacks on smartcards
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Tamper resistance: a cautionary note
WOEC'96 Proceedings of the 2nd conference on Proceedings of the Second USENIX Workshop on Electronic Commerce - Volume 2
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
RIJID: random code injection to mask power analysis based side channel attacks
Proceedings of the 44th annual Design Automation Conference
A smart random code injection to mask power analysis based side channel attacks
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Dependable and Secure Computing
Securing Designs against Scan-Based Side-Channel Attacks
IEEE Transactions on Dependable and Secure Computing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A bi-channel voltage regulator protecting smart cards against power analysis attacks
Analog Integrated Circuits and Signal Processing
Novel physical unclonable function with process and environmental variations
Proceedings of the Conference on Design, Automation and Test in Europe
A general power model of differential power analysis attacks to static logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The effectiveness of a current flattening circuit as countermeasure against DPA attacks
Microelectronics Journal
A countermeasure against power analysis attacks for FSR-based stream ciphers
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
FinFET-Based Power Management for Improved DPA Resistance with Low Overhead
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Three-phase dual-rail pre-charge logic
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
An architectural countermeasure against power analysis attacks for FSR-Based stream ciphers
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling
ACM Transactions on Embedded Computing Systems (TECS)
Randomized Instruction Injection to Counter Power Analysis Attacks
ACM Transactions on Embedded Computing Systems (TECS)
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There are several attacks that exploit the presence of side channels in hardware implementations of cryptographic algorithms to extract secret data. Differential Power Analysis (DPA) and Simple Power Analysis (SPA) attacks sense the power consumption of the hardware to extract the secret cryptographic key. These attacks either directly examine the power traces or carry out statistical operations on the power traces obtained from the hardware while executing the cryptographic algorithm. This paper presents a circuit that can be added to crypto-hardware to suppress information leakage through the power supply pin side channel. We discuss the design, simulation results and the limitations of the suppression circuit. We show that this countermeasure significantly increases the number of power trace samples required to undertake a DPA attack. The countermeasure does not require any assumptions about the design of the hardware under protection.