Use of elliptic curves in cryptography
Lecture notes in computer sciences; 218 on Advances in cryptology---CRYPTO 85
Available instruction-level parallelism for superscalar and superpipelined machines
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Parallel processing: a smart compiler and a dumb machine
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
Advanced Computer Architectures
Advanced Computer Architectures
Towards Sound Approaches to Counteract Power-Analysis Attacks
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
CRYPTO '96 Proceedings of the 16th Annual International Cryptology Conference on Advances in Cryptology
Low Cost Attacks on Tamper Resistant Devices
Proceedings of the 5th International Workshop on Security Protocols
DES and Differential Power Analysis (The "Duplication" Method)
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Random Register Renaming to Foil DPA
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Design principles for tamper-resistant smartcard processors
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Tamper resistance: a cautionary note
WOEC'96 Proceedings of the 2nd conference on Proceedings of the Second USENIX Workshop on Electronic Commerce - Volume 2
Random Register Renaming to Foil DPA
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Current flattening in software and hardware for security applications
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks
IEEE Transactions on Dependable and Secure Computing
Current mask generation: a transistor level security against DPA attacks
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Power-smart system-on-chip architecture for embedded cryptosystems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Nondeterministic Multithreading
IEEE Transactions on Computers
RIJID: random code injection to mask power analysis based side channel attacks
Proceedings of the 44th annual Design Automation Conference
A smart random code injection to mask power analysis based side channel attacks
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Non-deterministic processors: FPGA-based analysis of area, performance and security
WESS '09 Proceedings of the 4th Workshop on Embedded Systems Security
SCA-resistant embedded processors: the next generation
Proceedings of the 26th Annual Computer Security Applications Conference
Can code polymorphism limit information leakage?
WISTP'11 Proceedings of the 5th IFIP WG 11.2 international conference on Information security theory and practice: security and privacy of mobile devices in wireless communication
An evaluation of hash functions on a power analysis resistant processor architecture
WISTP'11 Proceedings of the 5th IFIP WG 11.2 international conference on Information security theory and practice: security and privacy of mobile devices in wireless communication
A first step towards automatic application of power analysis countermeasures
Proceedings of the 48th Design Automation Conference
An architecture-independent instruction shuffler to protect against side-channel attacks
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Implementation and evaluation of an SCA-resistant embedded processor
CARDIS'11 Proceedings of the 10th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Randomized Instruction Injection to Counter Power Analysis Attacks
ACM Transactions on Embedded Computing Systems (TECS)
The schedulability of AES as a countermeasure against side channel attacks
SPACE'12 Proceedings of the Second international conference on Security, Privacy, and Applied Cryptography Engineering
Shuffling against side-channel attacks: a comprehensive study with cautionary note
ASIACRYPT'12 Proceedings of the 18th international conference on The Theory and Application of Cryptology and Information Security
| Hi-index | 0.00 |
New techniques have been discovered to find the secret keys stored in smart-cards. These techniques have caused concern for they can allow people to recharge their smartcards (in effect printing money), or illegally use phone or digital TV services. We propose a new processor design which will counteract these techniques. By randomising the instruction stream being executed by the processor we can hide the secret key stored in a smartcard. The extension we propose can be added to existing processors, and is transparent to the algorithm.