The Design of Rijndael
ACISP '01 Proceedings of the 6th Australasian Conference on Information Security and Privacy
Instruction Stream Mutation for Non-Deterministic Processors
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Security as a new dimension in embedded system design
Proceedings of the 41st annual Design Automation Conference
Security in embedded systems: Design challenges
ACM Transactions on Embedded Computing Systems (TECS)
Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)
Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)
Nondeterministic Multithreading
IEEE Transactions on Computers
RIJID: random code injection to mask power analysis based side channel attacks
Proceedings of the 44th annual Design Automation Conference
On second-order differential power analysis
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
An AES smart card implementation resistant to power analysis attacks
ACNS'06 Proceedings of the 4th international conference on Applied Cryptography and Network Security
SCA-resistant embedded processors: the next generation
Proceedings of the 26th Annual Computer Security Applications Conference
A countermeasure against power analysis attacks for FSR-based stream ciphers
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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Finding a suitable balance between performance and physical security can be a significant challenge when implementing cryptographic software. Although asymmetric primitives often afford inexpensive countermeasures against side-channel attack as a result of flexibility in the underlying mathematics, symmetric primitives are generally not as fortunate. The previously proposed NONDET processor architecture attempts to address this problem by securing generic workloads via micro-architectural countermeasures against DPA attack; in this paper we present the first concrete investigation of NONDET using AES as a case study. Our results indicate that versus an implementation of AES with no countermeasures, NONDET can significantly increase the number of acquisitions required for a successful DPA attack. Alternatively, versus an implementation using traditional software-based countermeasures such as randomisation and masking, NONDET can produce significant improvements in performance and memory footprint.