Current mask generation: a transistor level security against DPA attacks
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Nondeterministic Multithreading
IEEE Transactions on Computers
RIJID: random code injection to mask power analysis based side channel attacks
Proceedings of the 44th annual Design Automation Conference
A smart random code injection to mask power analysis based side channel attacks
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Non-deterministic processors: FPGA-based analysis of area, performance and security
WESS '09 Proceedings of the 4th Workshop on Embedded Systems Security
A first step towards automatic application of power analysis countermeasures
Proceedings of the 48th Design Automation Conference
Generic side-channel countermeasures for reconfigurable devices
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Randomized Instruction Injection to Counter Power Analysis Attacks
ACM Transactions on Embedded Computing Systems (TECS)
The schedulability of AES as a countermeasure against side channel attacks
SPACE'12 Proceedings of the Second international conference on Security, Privacy, and Applied Cryptography Engineering
Efficient removal of random delays from embedded software implementations using hidden markov models
CARDIS'12 Proceedings of the 11th international conference on Smart Card Research and Advanced Applications
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Differential power analysis (DPA) has become a real-world threat to the security of crypto-graphic hardware devices such as smart-cards. By using cheap and readily available equipment, attacks can easily compromise algorithms running on these devices in a non-invasive manner. Adding non-determinism to the execution of cryptographic algorithms has been proposed as a defence against these attacks. One way of achieving this non-determinism is to introduce random additional operations to the algorithm which produce noise in the power profile of the device. We describe the addition of a specialised processor pipeline stage which increases the level of potential non-determinism and hence guards against the revelation of secret information.