ACISP '01 Proceedings of the 6th Australasian Conference on Information Security and Privacy
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
CRYPTO '96 Proceedings of the 16th Annual International Cryptology Conference on Advances in Cryptology
On Boolean and Arithmetic Masking against Differential Power Analysis
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
Random Register Renaming to Foil DPA
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Instruction Stream Mutation for Non-Deterministic Processors
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Improving Smart Card Security Using Self-Timed Circuits
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
SBAC-PAD '04 Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing
Model and Design of Bipolar and Mos Current-Mode Logic: CML, Ecl and Scl Digital Circuits
Model and Design of Bipolar and Mos Current-Mode Logic: CML, Ecl and Scl Digital Circuits
Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)
Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)
A generic standard cell design methodology for differential circuit styles
Proceedings of the conference on Design, automation and test in Europe
Power Analysis Resistant AES Implementation with Instruction Set Extensions
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Information Theoretic Evaluation of Side-Channel Resistant Logic Styles
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
PRESENT: An Ultra-Lightweight Block Cipher
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Transactions on Computational Science IV
A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks
EUROCRYPT '09 Proceedings of the 28th Annual International Conference on Advances in Cryptology: the Theory and Applications of Cryptographic Techniques
Instruction set extensions for efficient AES implementation on 32-bit processors
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Masking at gate level in the presence of glitches
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
SCA-resistant embedded processors: the next generation
Proceedings of the 26th Annual Computer Security Applications Conference
A formal study of power variability issues and side-channel attacks for nanoscale devices
EUROCRYPT'11 Proceedings of the 30th Annual international conference on Theory and applications of cryptographic techniques: advances in cryptology
A first step towards automatic application of power analysis countermeasures
Proceedings of the 48th Design Automation Conference
Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library
Proceedings of the 48th Design Automation Conference
Implementation and evaluation of an SCA-resistant embedded processor
CARDIS'11 Proceedings of the 10th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Randomized Instruction Injection to Counter Power Analysis Attacks
ACM Transactions on Embedded Computing Systems (TECS)
POWER-MODES: POWer-EmulatoR- and MOdel-Based DEpendability and Security Evaluations
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
Journal of Information Security and Applications
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Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been proposed as an alternative to CMOS. However, they should only be used sparingly, since their area and power consumption are both significantly larger than for CMOS. We propose to augment a processor, realized in CMOS, with custom instruction set extensions, designed with security and performance as the primary objectives, that are realized in a protected logic. We have developed a design flow based on standard CAD tools that can automatically synthesize and place-and-route such hybrid designs. The flow is integrated into a simulation and evaluation environment to quantify the security achieved on a sound basis. Using MCML logic as a case study, we have explored different partitions of the PRESENT block cipher between protected and unprotected logic. This experiment illustrates the tradeoff between the type and amount of application-level functionality implemented in protected logic and the level of security achieved by the design. Our design approach and evaluation tools are generic and could be used to partition any algorithm using any protected logic style.