CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
CRYPTO '96 Proceedings of the 16th Annual International Cryptology Conference on Advances in Cryptology
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Design Method for Constant Power Consumption of Differential Logic Circuits
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Simulation models for side-channel information leaks
Proceedings of the 42nd annual Design Automation Conference
Template attacks in principal subspaces
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Towards security limits in side-channel attacks
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Security evaluation of DPA countermeasures using dual-rail pre-charge logic style
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Side-channel leakage of masked CMOS gates
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Masking at gate level in the presence of glitches
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Security evaluation against electromagnetic analysis at design time
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
The “backend duplication” method
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Formally Bounding the Side-Channel Leakage in Unknown-Message Attacks
ESORICS '08 Proceedings of the 13th European Symposium on Research in Computer Security: Computer Security
A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks
EUROCRYPT '09 Proceedings of the 28th Annual International Conference on Advances in Cryptology: the Theory and Applications of Cryptographic Techniques
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
A Comparative Study of Mutual Information Analysis under a Gaussian Assumption
Information Security Applications
On side-channel resistant block cipher usage
ISC'10 Proceedings of the 13th international conference on Information security
WISA'10 Proceedings of the 11th international conference on Information security applications
Automatically deriving information-theoretic bounds for adaptive side-channel attacks
Journal of Computer Security
Generic side-channel countermeasures for reconfigurable devices
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Information theoretic and security analysis of a 65-nanometer DDSLL AES S-box
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Fresh re-keying: security against side-channel and fault attacks for low-cost devices
AFRICACRYPT'10 Proceedings of the Third international conference on Cryptology in Africa
Randomized Instruction Injection to Counter Power Analysis Attacks
ACM Transactions on Embedded Computing Systems (TECS)
A novel circuit design methodology to reduce side channel leakage
SPACE'12 Proceedings of the Second international conference on Security, Privacy, and Applied Cryptography Engineering
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We propose to apply an information theoretic metric to the evaluation of side-channel resistant logic styles. Due to the long design and development time required for the physical evaluation of such hardware countermeasures, our analysis is based on simulations. Although they do not aim to replace the need of actual measurements, we show that simulations can be used as a meaningful first step in the validation chain of a cryptographic product. For illustration purposes, we apply our methodology to gate-level simulations of different logic styles and stress that it allows a significant improvement of the previously considered evaluation methods. In particular, our results allow putting forward the respective strengths and weaknesses of actual countermeasures and determining to which extent they can practically lead to secure implementations (with respect to a noise parameter), if adversaries were provided with simulation-based side-channel traces. Most importantly, the proposed methodology can be straightforwardly adapted to adversaries provided with any other kind of leakage traces (including physical ones).