Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Examining Smart-Card Security under the Threat of Power Analysis Attacks
IEEE Transactions on Computers
Towards Sound Approaches to Counteract Power-Analysis Attacks
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
DES and Differential Power Analysis (The "Duplication" Method)
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Improving Smart Card Security Using Self-Timed Circuits
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Side-channel leakage of masked CMOS gates
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Design methods for security and trust
Proceedings of the conference on Design, automation and test in Europe
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 44th annual Design Automation Conference
Secure FPGA circuits using controlled placement and routing
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Power Analysis Attacks and Countermeasures
IEEE Design & Test
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
IEEE Design & Test
A secure and low-energy logic style using charge recovery approach
Proceedings of the 13th international symposium on Low power electronics and design
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Masking and Dual-Rail Logic Don't Add Up
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
DPA-Resistance Without Routing Constraints?
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Information Theoretic Evaluation of Side-Channel Resistant Logic Styles
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Physical Design of FPGA Interconnect to Prevent Information Leakage
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Divided Backend Duplication Methodology for Balanced Dual Rail Routing
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A Practical DPA Countermeasure with BDD Architecture
CARDIS '08 Proceedings of the 8th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Dual-rail transition logic: A logic style for counteracting power analysis attacks
Computers and Electrical Engineering
Security Evaluations of MRSL and DRSL Considering Signal Delays
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches
Information Security and Cryptology --- ICISC 2008
Practical Attacks on Masked Hardware
CT-RSA '09 Proceedings of the The Cryptographers' Track at the RSA Conference 2009 on Topics in Cryptology
Fault Analysis Attack against an AES Prototype Chip Using RSL
CT-RSA '09 Proceedings of the The Cryptographers' Track at the RSA Conference 2009 on Topics in Cryptology
Vulnerability modeling of cryptographic hardware to power analysis attacks
Integration, the VLSI Journal
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
On the security of RFID devices against implementation attacks
International Journal of Security and Networks
Power analysis attacks on MDPL and DRSL implementations
ICISC'07 Proceedings of the 10th international conference on Information security and cryptology
Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A new remote keyless entry system resistant to power analysis attacks
ICICS'09 Proceedings of the 7th international conference on Information, communications and signal processing
Evaluation of Random Delay Insertion against DPA on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation
Proceedings of the Conference on Design, Automation and Test in Europe
Countering early evaluation: an approach towards robust dual-rail precharge logic
WESS '10 Proceedings of the 5th Workshop on Embedded Systems Security
Implementing virtual secure circuit using a custom-instruction approach
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Power analysis of single-rail storage elements as used in MDPL
ICISC'09 Proceedings of the 12th international conference on Information security and cryptology
Lightweight cryptography and DPA countermeasures: a survey
FC'10 Proceedings of the 14th international conference on Financial cryptograpy and data security
Exploiting dual-output programmable blocks to balance secure dual-rail logics
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Pushing the limits: a very compact and a threshold implementation of AES
EUROCRYPT'11 Proceedings of the 30th Annual international conference on Theory and applications of cryptographic techniques: advances in cryptology
Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library
Proceedings of the 48th Design Automation Conference
A comprehensive evaluation of mutual information analysis using a fair evaluation framework
CRYPTO'11 Proceedings of the 31st annual conference on Advances in cryptology
First principal components analysis: a new side channel distinguisher
ICISC'10 Proceedings of the 13th international conference on Information security and cryptology
Information theoretic and security analysis of a 65-nanometer DDSLL AES S-box
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Threshold implementations against side-channel attacks and glitches
ICICS'06 Proceedings of the 8th international conference on Information and Communications Security
Optically enhanced position-locked power analysis
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Pinpointing the side-channel leakage of masked AES hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Three-phase dual-rail pre-charge logic
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Dual-rail random switching logic: a countermeasure to reduce side channel leakage
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Security evaluation of DPA countermeasures using dual-rail pre-charge logic style
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Differential power analysis: a serious threat for FPGA security
International Journal of Internet Technology and Secured Transactions
Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Successfully attacking masked AES hardware implementations
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Side-Channel leakage across borders
CARDIS'10 Proceedings of the 9th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Application
Implementation and evaluation of an SCA-resistant embedded processor
CARDIS'11 Proceedings of the 10th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
COSADE'12 Proceedings of the Third international conference on Constructive Side-Channel Analysis and Secure Design
LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Threshold implementations of all 3×3 and 4×4 s-boxes
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
A novel circuit design methodology to reduce side channel leakage
SPACE'12 Proceedings of the Second international conference on Security, Privacy, and Applied Cryptography Engineering
An EDA-friendly protection scheme against side-channel attacks
Proceedings of the Conference on Design, Automation and Test in Europe
A flip-flop for the DPA resistant three-phase dual-rail pre-charge logic family
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Masked dual-rail precharge logic encounters state-of-the-art power analysis methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A low-entropy first-degree secure provable masking scheme for resource-constrained devices
Proceedings of the Workshop on Embedded Systems Security
On 3-share threshold implementations for 4-bit s-boxes
COSADE'13 Proceedings of the 4th international conference on Constructive Side-Channel Analysis and Secure Design
Stealthy dopant-level hardware trojans
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
Impact of dual placement and routing on WDDL netlist security in FPGA
International Journal of Reconfigurable Computing
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During the last years, several logic styles that counteract side-channel attacks have been proposed. They all have in common that their level of resistance heavily depends on implementation constraints that are costly to satisfy. For example, the capacitive load of complementary wires in an integrated circuit may need to be balanced. This article describes a novel side-channel analysis resistant logic style called MDPL that completely avoids such constraints. It is a masked and dual-rail pre-charge logic style and can be implemented using common CMOS standard cell libraries. This makes MDPL perfectly suitable for semi-custom designs.