Masked dual-rail precharge logic encounters state-of-the-art power analysis methods

Authors:
Amir Moradi;Mario Kirschbaum;Thomas Eisenbarth;Christof Paar
Affiliations:
Horst Görtz Institute for IT-Security, Ruhr University Bochum, Bochum, Germany;Institute for Applied Information Processing and Communications, Graz University of Technology, Graz, Austria;Department of Mathematical Sciences, Florida Atlantic University, FL;Horst Görtz Institute for IT-Security, Ruhr University Bochum, Bochum, Germany
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

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Abstract

Latest evaluation of the state-of-the-art iMDPL logic style has shown small information leakage compared to its predecessor version MDPL. Concurrently, new advanced power analysis attacks specifically targeting iMDPL have been proposed. Up to now, these attacks are purely theoretic and have not been applied to an implementation. We present a comprehensive analysis of iMDPL, backed by real measurements collected from a 180 nm iMDPL prototype chip. We thoroughly study the extent of remaining information leakage of iMDPL by applying all relevant attacks. Our investigation shows the vulnerability of the target device, a standalone AES core, to several of the advanced attack methods. In comparison to conventional power analysis attacks, the advanced attacks need less power measurements to obtain meaningful results. With the help of logic level simulations routing imbalances between complementary mask trees are identified as a major source of leakage.