Side-channel leakage of masked CMOS gates
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Improved higher-order side-channel attacks with FPGA experiments
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Prototype IC with WDDL and differential routing – DPA resistance assessment
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
DPA leakage models for CMOS logic circuits
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Power Analysis Attacks and Countermeasures
IEEE Design & Test
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
IEEE Design & Test
Masking and Dual-Rail Logic Don't Add Up
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
DPA-Resistance Without Routing Constraints?
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Practical Attacks on Masked Hardware
CT-RSA '09 Proceedings of the The Cryptographers' Track at the RSA Conference 2009 on Topics in Cryptology
Fault Analysis Attack against an AES Prototype Chip Using RSL
CT-RSA '09 Proceedings of the The Cryptographers' Track at the RSA Conference 2009 on Topics in Cryptology
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Power variance analysis breaks a masked ASIC implementation of AES
Proceedings of the Conference on Design, Automation and Test in Europe
Power analysis of single-rail storage elements as used in MDPL
ICISC'09 Proceedings of the 12th international conference on Information security and cryptology
Threshold implementations against side-channel attacks and glitches
ICICS'06 Proceedings of the 8th international conference on Information and Communications Security
Security evaluation of a DPA-Resistant s-box based on the fourier transform
ICICS'09 Proceedings of the 11th international conference on Information and Communications Security
Implementation and evaluation of an SCA-resistant embedded processor
CARDIS'11 Proceedings of the 10th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Masked dual-rail precharge logic encounters state-of-the-art power analysis methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On measurable side-channel leaks inside ASIC design primitives
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
Impact of dual placement and routing on WDDL netlist security in FPGA
International Journal of Reconfigurable Computing
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Random switching logic (RSL) has been proposed as an efficient countermeasure to mitigate power analysis. The logic style equalizes the output transition probabilities using a random mask-bit. This manuscript, however, will show a successful attack against RSL. The single mask-bit can only add one bit of entropy to the information content of the overall power consumption variations and can very easily be deduced from the power consumption. Once the mask-bit is known, the a posteriori probabilities of the output transitions are not equal anymore and a power analysis can be mounted. A threshold filter suffices to remove the additional bit of information.