Power variance analysis breaks a masked ASIC implementation of AES

Authors:
Yang Li;Kazuo Sakiyama;Lejla Batina;Daisuke Nakatsu;Kazuo Ohta
Affiliations:
The University of Electro-Communications, Tokyo, Japan;The University of Electro-Communications, Tokyo, Japan;Radboud University Nijmegen, Nijmegen, The Netherlands and Katholieke Universiteit Leuven, Leuven, Belgium;The University of Electro-Communications, Tokyo, Japan;The University of Electro-Communications, Tokyo, Japan
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2010

Citing 11
Cited 2

Towards Sound Approaches to Counteract Power-Analysis Attacks

CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Differential Power Analysis

CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Statistics and Secret Leakage

FC '00 Proceedings of the 4th International Conference on Financial Cryptography
Using Second-Order Power Analysis to Attack DPA Resistant Software

CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
An Optimized S-Box Circuit Architecture for Low Power AES Design

CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)

Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)
Mutual Information Analysis

CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Fault Analysis Attack against an AES Prototype Chip Using RSL

CT-RSA '09 Proceedings of the The Cryptographers' Track at the RSA Conference 2009 on Topics in Cryptology
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques

CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Changing the odds against masked logic

SAC'06 Proceedings of the 13th international conference on Selected areas in cryptography
Improved higher-order side-channel attacks with FPGA experiments

CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems

First principal components analysis: a new side channel distinguisher

ICISC'10 Proceedings of the 13th international conference on Information security and cryptology
High-order timing attacks

Proceedings of the First Workshop on Cryptography and Security in Computing Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

To obtain a better trade-off between cost and security, practical DPA countermeasures are not likely to deploy full masking that uses one distinct mask bit for each signal. A common approach is to use the same mask on several instances of an algorithm. This paper proposes a novel power analysis method called Power Variance Analysis (PVA) to reveal the danger of such implementations. PVA uses the fact that the side-channel leakage of parallel circuits has a big variance when they are given the same but random inputs. This paper introduces the basic principle of PVA and a series of PVA experiments including a successful PVA attack against a prototype RSL-AES implemented on SASEBO-R.