Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases
Information and Computation
Low Power Digital CMOS Design
Efficient Algorithms for Elliptic Curve Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
A Compact Rijndael Hardware Architecture with S-Box Optimization
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m)
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Two Methods of Rijndael Implementation in Reconfigurable Hardware
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
High Performance Single-Chip FPGA Rijndael Algorithm Implementations
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Power-efficient ASIC synthesis of cryptographic sboxes
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Area, delay, and power characteristics of standard-cell implementations of the AES S-Box
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Vortex: A New Family of One-Way Hash Functions Based on AES Rounds and Carry-Less Multiplication
ISC '08 Proceedings of the 11th international conference on Information Security
An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Journal of Electronic Testing: Theory and Applications
On the ability of AES S-boxes to secure against correlation power analysis
ISPEC'07 Proceedings of the 3rd international conference on Information security practice and experience
A very compact "Perfectly masked" S-box for AES
ACNS'08 Proceedings of the 6th international conference on Applied cryptography and network security
Implementation and benchmarking of hardware accelerators for ciphering in LTE terminals
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
An efficient design of security accelerator for IEEE 802.15.4 wireless sensor networks
CCNC'10 Proceedings of the 7th IEEE conference on Consumer communications and networking conference
Proceedings of the ACM SIGCOMM 2010 conference
Power variance analysis breaks a masked ASIC implementation of AES
Proceedings of the Conference on Design, Automation and Test in Europe
Mixed bases for efficient inversion in F((22)2)2 and conversion matrices of SubBytes of AES
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Pinpointing the side-channel leakage of masked AES hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Security evaluation of DPA countermeasures using dual-rail pre-charge logic style
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
NanoCMOS-molecular realization of rijndael
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Small size, low power, side channel-immune AES coprocessor: design and synthesis results
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Secure AES hardware module for resource constrained devices
ESAS'04 Proceedings of the First European conference on Security in Ad-hoc and Sensor Networks
Area, delay, and power characteristics of standard-cell implementations of the AES s-box
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
The smallest ARIA module with 16-bit architecture
ICISC'06 Proceedings of the 9th international conference on Information Security and Cryptology
mCrypton – a lightweight block cipher for security of low-cost RFID tags and sensors
WISA'05 Proceedings of the 6th international conference on Information Security Applications
Construction of S8 Liu J S-boxes and their applications
Computers & Mathematics with Applications
LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Performance and security evaluation of AES s-box-based glitch PUFs on FPGAs
SPACE'12 Proceedings of the Second international conference on Security, Privacy, and Applied Cryptography Engineering
Revealing side-channel issues of complex circuits by enhanced leakage models
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
Integration, the VLSI Journal
Exploring the relations between fault sensitivity and power consumption
COSADE'13 Proceedings of the 4th international conference on Constructive Side-Channel Analysis and Secure Design
AES side-channel countermeasure using random tower field constructions
Designs, Codes and Cryptography
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Reducing the power consumption of AES circuits is a critical problem when the circuits are used in low power embedded systems. We found the S-Boxes consume much of the total AES circuit power and the power for an S-Box is mostly determined by the number of dynamic hazards. In this paper, we propose a low-power S-Box circuit architecture: a multi-stage PPRM architecture over composite fields. In this S-Box, (i) the signal arrival times of gates are as close as possible if the depths of the gates from the primary inputs are the same, and (ii) the hazard-transparent XOR gates are located after the other gates that may block the hazards. A low power consumption of 29 碌W at 10 MHz using 0.13 碌m 1.5V CMOS technology was achieved, while the consumptions of the BDD, SOP, and composite field S-Boxes are 275, 95, and 136 碌W, respectively.