Introduction to finite fields and their applications
Introduction to finite fields and their applications
A Fast New DES Implementation in Software
FSE '97 Proceedings of the 4th International Workshop on Fast Software Encryption
Fast arithmetic architectures for public-key algorithms over Galois fields GF((2n)m)
EUROCRYPT'97 Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques
An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
Security of a Wide Trail Design
INDOCRYPT '02 Proceedings of the Third International Conference on Cryptology: Progress in Cryptology
An Optimized S-Box Circuit Architecture for Low Power AES Design
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Efficient Software Implementation of AES on 32-Bit Platforms
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
On the Power of Bitslice Implementation on Intel Core2 Processor
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Vortex: A New Family of One-Way Hash Functions Based on AES Rounds and Carry-Less Multiplication
ISC '08 Proceedings of the 11th international conference on Information Security
Using Normal Bases for Compact Hardware Implementations of the AES S-Box
SCN '08 Proceedings of the 6th international conference on Security and Cryptography for Networks
Accelerating AES with Vector Permute Instructions
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Proceedings of the ACM SIGCOMM 2010 conference
Secure multiplicative masking of power functions
ACNS'10 Proceedings of the 8th international conference on Applied cryptography and network security
Inv mix column decomposition and multilevel resource sharing in AES implementations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast and provably secure higher-order masking of AES S-box
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Provably secure s-box implementation based on fourier transform
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
How far can we go on the x64 processors?
FSE'06 Proceedings of the 13th international conference on Fast Software Encryption
A systematic evaluation of compact hardware implementations for the rijndael s-box
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Efficient AES implementations on ASICs and FPGAs
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Small size, low power, side channel-immune AES coprocessor: design and synthesis results
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Representations and rijndael descriptions
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Secure AES hardware module for resource constrained devices
ESAS'04 Proceedings of the First European conference on Security in Ad-hoc and Sensor Networks
Bitslice implementation of AES
CANS'06 Proceedings of the 5th international conference on Cryptology and Network Security
A bit-slice implementation of the whirlpool hash function
CT-RSA'07 Proceedings of the 7th Cryptographers' track at the RSA conference on Topics in Cryptology
A first-order leak-free masking countermeasure
CT-RSA'12 Proceedings of the 12th conference on Topics in Cryptology
Secure and fast implementations of two involution ciphers
NordSec'10 Proceedings of the 15th Nordic conference on Information Security Technology for Applications
Construction of optimum composite field architecture for compact high-throughput AES S-boxes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selective secure error correction on SPIHT coefficients for pervasive wireless visual network
International Journal of Ad Hoc and Ubiquitous Computing
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
Integration, the VLSI Journal
AES side-channel countermeasure using random tower field constructions
Designs, Codes and Cryptography
Analyzing and comparing the AES architectures for their power consumption
Journal of Intelligent Manufacturing
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We explore the use of subfield arithmetic for efficient implementations of Galois Field arithmetic especially in the context of the Rijndael block cipher. Our technique involves mapping field elements to a composite field representation. We describe how to select a representation which minimizes the computation cost of the relevant arithmetic, taking into account the cost of the mapping as well. Our method results in a very compact and fast gate circuit for Rijndael encryption. In conjunction with bit-slicing techniques applied to newly proposed parallelizable modes of operation, our circuit leads to a high-performance software implementation for Rijndael encryption which offers significant speedup compared to previously reported implementations.