The Design of Rijndael
A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
CT-RSA 2001 Proceedings of the 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA
An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
Efficient Algorithms for Elliptic Curve Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
Security of a Wide Trail Design
INDOCRYPT '02 Proceedings of the Third International Conference on Cryptology: Progress in Cryptology
A Compact Rijndael Hardware Architecture with S-Box Optimization
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Two Methods of Rijndael Implementation in Reconfigurable Hardware
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
High Performance Single-Chip FPGA Rijndael Algorithm Implementations
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Dual-Field Arithmetic Unit for GF(p) and GF(2m)
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Novel Pipelined Threads Architecture for AES Encryption Algorithm
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Area, delay, and power characteristics of standard-cell implementations of the AES S-Box
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
On the Power of Bitslice Implementation on Intel Core2 Processor
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Using Normal Bases for Compact Hardware Implementations of the AES S-Box
SCN '08 Proceedings of the 6th international conference on Security and Cryptography for Networks
Compact and secure design of masked AES S-box
ICICS'07 Proceedings of the 9th international conference on Information and communications security
Proceedings of the ACM SIGCOMM 2010 conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A formal study of power variability issues and side-channel attacks for nanoscale devices
EUROCRYPT'11 Proceedings of the 30th Annual international conference on Theory and applications of cryptographic techniques: advances in cryptology
Information theoretic and security analysis of a 65-nanometer DDSLL AES S-box
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Area, delay, and power characteristics of standard-cell implementations of the AES s-box
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
RFIDSec'11 Proceedings of the 7th international conference on RFID Security and Privacy
Construction of S8 Liu J S-boxes and their applications
Computers & Mathematics with Applications
Towards green cryptography: a comparison of lightweight ciphers from the energy viewpoint
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
Construction of optimum composite field architecture for compact high-throughput AES S-boxes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
Integration, the VLSI Journal
Strong PUFs and their (physical) unpredictability: a case study with power PUFs
Proceedings of the Workshop on Embedded Systems Security
SN-SEC: a secure wireless sensor platform with hardware cryptographic primitives
Personal and Ubiquitous Computing
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This work proposes a compact implementation of the AES S-box using composite field arithmetic in GF(((22)2)2). It describes a systematic exploration of different choices for the irreducible polynomials that generate the extension fields. It also examines all possible transformation matrices that map one field representation to another. We show that the area of Satoh's S-box, which is the most compact to our knowledge, is at least 5% away from an optimal solution. We implemented this optimal solution and Satoh's design using a 0.18 μm standard cell library.