Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Design of Rijndael
8 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
An Adaptive Cryptographic Engine for IPSec Architectures
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Security on FPGAs: State-of-the-art implementations and attacks
ACM Transactions on Embedded Computing Systems (TECS)
High-speed VLSI architectures for the AES algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A configurable AES processor for enhanced security
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Accelerated AES implementations via generalized instruction set extensions
Journal of Computer Security - The Third IEEE International Symposium on Security in Networks and Distributed Systems
Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration
Microelectronics Journal
DSPs, BRAMs, and a Pinch of Logic: Extended Recipes for AES on FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
Integration, the VLSI Journal
A very compact "Perfectly masked" S-box for AES
ACNS'08 Proceedings of the 6th international conference on Applied cryptography and network security
Modified AES using chaotic key generator for satellite imagery encryption
ICIC'09 Proceedings of the 5th international conference on Emerging intelligent computing technology and applications
Novel approach design of elliptic curve cryptography implementation in VLSI
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
Single- and multi-core configurable AES architectures for flexible security
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance GHASH function for long messages
ACNS'10 Proceedings of the 8th international conference on Applied cryptography and network security
Enhancing the performance of symmetric-key cryptography via instruction set extensions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-speed and area efficient hardware implementation of AES-128 encryption standard
MIV'05 Proceedings of the 5th WSEAS international conference on Multimedia, internet & video technologies
FPGA implementation and performance evaluation of a high throughput crypto coprocessor
Journal of Parallel and Distributed Computing
Design of an ultra high speed AES processor for next generation IT security
Computers and Electrical Engineering
A systematic evaluation of compact hardware implementations for the rijndael s-box
CT-RSA'05 Proceedings of the 2005 international conference on Topics in Cryptology
Configurable computing for high-security/high-performance ambient systems
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
AES on FPGA from the fastest to the smallest
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
An efficient design of CCMP for robust security network
ICISC'05 Proceedings of the 8th international conference on Information Security and Cryptology
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A fully pipelined implementation of the Advanced Encryption Standard encryption algorithm with 128-bit input and key length (AES-128) was implemented on Xilinx' Virtex-E and Virtex-II devices. The design is called SIG-AES-E and it implements the S-boxes combinatorially and thus requires no internal memory. It is concluded, that SIG-AES-E is faster than other published FPGA-based implementations of the AES-128 encryption algorithm.