A high-speed and area efficient hardware implementation of AES-128 encryption standard

Authors:
A. Brokalakis;H. Michail;A. Kakarountas;E. Fotopoulou;A. Milidonis;G. Theodoridis;C. Goutis
Affiliations:
Computer Engineering & Informatics Department, University of Patras, Patra, Greece;Electrical & Computer Engineering Department, University of Patras, Patra, Greece;Electrical & Computer Engineering Department, University of Patras, Patra, Greece;Electrical & Computer Engineering Department, University of Patras, Patra, Greece;Electrical & Computer Engineering Department, University of Patras, Patra, Greece;Department of Physics, Aristotle, University of Thesalloniki, Thesalloniki, Greece;Electrical & Computer Engineering Department, University of Patras, Patra, Greece
Venue:
MIV'05 Proceedings of the 5th WSEAS international conference on Multimedia, internet & video technologies
Year:
2005

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Abstract

The Advanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address security issues. In this paper, a high throughput area efficient FPGA implementation of the latter cryptographic primitive is proposed. It presents the highest performance (in terms of throughput) among competitive academic and commercial implementations. Using a Virtex-II device, a 1.94Gbps throughput is achieved, while the memory usage remains low (8 BlockRAMs) and the CLB coverage moderate.