The Design of Rijndael
An ASIC Implementation of the AES SBoxes
CT-RSA '02 Proceedings of the The Cryptographer's Track at the RSA Conference on Topics in Cryptology
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
Secure scan: a design-for-test architecture for crypto chips
Proceedings of the 42nd annual Design Automation Conference
On-demand design service innovations
IBM Journal of Research and Development
A High Performance Sub-Pipelined Architecture for AES
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A compact FPGA implementation of the hash function whirlpool
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A configurable AES processor for enhanced security
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Totally Self-Checking S-box Architecture for the Advanced Encryption Standard
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Simple Error Detection Methods for Hardware Implementation of Advanced Encryption Standard
IEEE Transactions on Computers
Reconfigurable system for high-speed and diversified AES using FPGA
Microprocessors & Microsystems
DPA-Resistance Without Routing Constraints?
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Comparative Evaluation of Rank Correlation Based DPA on an AES Prototype Chip
ISC '08 Proceedings of the 11th international conference on Information Security
A Secure Test Technique for Pipelined Advanced Encryption Standard
IEICE - Transactions on Information and Systems
Practical Attacks on Masked Hardware
CT-RSA '09 Proceedings of the The Cryptographers' Track at the RSA Conference 2009 on Topics in Cryptology
Relating Boolean gate truth tables to one-way functions
Integrated Computer-Aided Engineering
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Lightweight mix columns implementation for AES
AIC'09 Proceedings of the 9th WSEAS international conference on Applied informatics and communications
Journal of Electronic Testing: Theory and Applications
Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications
Transactions on Data Privacy
Efficient implementation of pseudorandom functions for electronic seal protection protocols
WISA'06 Proceedings of the 7th international conference on Information security applications: PartI
Single- and multi-core configurable AES architectures for flexible security
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Lightweight mix columns implementation for AES
MMACTEE'09 Proceedings of the 11th WSEAS international conference on Mathematical methods and computational techniques in electrical engineering
A high-speed and area efficient hardware implementation of AES-128 encryption standard
MIV'05 Proceedings of the 5th WSEAS international conference on Multimedia, internet & video technologies
Implementation of a cryptographic co-processor
ISP'07 Proceedings of the 6th WSEAS international conference on Information security and privacy
A hardware implementation of lightweight block cipher for ubiquitous computing security
KES'06 Proceedings of the 10th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I
Accelerating AES using instruction set extensions for elliptic curve cryptography
ICCSA'05 Proceedings of the 2005 international conference on Computational Science and Its Applications - Volume Part II
Block-Level storage security architectures
ICCSA'06 Proceedings of the 6th international conference on Computational Science and Its Applications - Volume Part I
Energy comparison of AES and SHA-1 for ubiquitous computing
EUC'06 Proceedings of the 2006 international conference on Emerging Directions in Embedded and Ubiquitous Computing
Efficient AES implementations on ASICs and FPGAs
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Small size, low power, side channel-immune AES coprocessor: design and synthesis results
AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Secure AES hardware module for resource constrained devices
ESAS'04 Proceedings of the First European conference on Security in Ad-hoc and Sensor Networks
Low power AES hardware architecture for radio frequency identification
IWSEC'06 Proceedings of the 1st international conference on Security
Side-Channel leakage across borders
CARDIS'10 Proceedings of the 9th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Application
Masked dual-rail precharge logic encounters state-of-the-art power analysis methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
Integration, the VLSI Journal
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This article presents a highly regular and scalable AES hardware architecture, suited for full-custom as well as for semi-custom design flows. Contrary to other publications, a complete architecture (even including CBC mode) that is scalable in terms of throughput and in terms of the used key size is described. Similarities of encryption and decryption are utilized to provide a high level of performance using only a relatively small area (10,799 gate equivalents for the standard configuration). This performance is reached by balancing the combinational paths of the design. No other published AES hardware architecture provides similar balancing or a comparable regularity. Implementations of the fastest configuration of the architecture provide a throughput of 241 Mbits/sec on a 0.6 \mum CMOS process using standard cells.