Implementation of a cryptographic co-processor

  • Authors:

  • A. P. Kakarountas;H. Michail

  • Affiliations:

  • Dpt. of Electrical & Computer Engineering, University of Patras, Patras, Greece;Dpt. of Electrical & Computer Engineering, University of Patras, Patras, Greece

  • Venue:
  • ISP'07 Proceedings of the 6th WSEAS international conference on Information security and privacy
  • Year:
  • 2007

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Abstract

In this paper a high-speed cryptographic co-processor, named HSSec, is presented. The core embeds two hash functions, SHA-1 and SHA-512, and the symmetric block cipher AES. The architecture of HSSec renders it suitable for widely spread applications with security demands. The presented coprocessor can be used inevery system integrating standards such as IPSec or the upcoming JPSec and P1619. The main characteristic of the proposed implementation is common use of the available resources, to minimize further area requirements. Additionally the cryptographic primitives can operate in parallel, providing high throughput whenever needed. Finally the system can operate in ECB or CBC modes. The HSSec co-processor has relatively small area and its performance reaches 1 Gbps (AES, SHA-1 and SHA-512) for XILINX's Virtex II FPGA family.