Lightweight mix columns implementation for AES

Authors:
Eslam Gamal Ahmed;Eman Shaaban;Mohamed Hashem
Affiliations:
Computer Systems Department, Faculty of Computer and Information Science, Ain Shams University, Cairo, Egypt;Computer Systems Department, Faculty of Computer and Information Science, Ain Shams University, Cairo, Egypt;Information System Department, Faculty of Computer and Information Science, Ain Shams University, Cairo, Egypt
Venue:
AIC'09 Proceedings of the 9th WSEAS international conference on Applied informatics and communications
Year:
2009

Citing 2
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A Highly Regular and Scalable AES Hardware Architecture

IEEE Transactions on Computers
Computer Security: Principles and Practice

Computer Security: Principles and Practice

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Abstract

Since the debut of the Advanced Encryption Standard (AES), it has been thoroughly studied by hardware designers with the goal of reducing the area and delay of the hardware implementation of this cryptosystem. This paper proposes an implementation of the AES mix columns operation. In this paper, a compact architecture for the AES mix columns operation and its inverse is presented. The hardware implementation is compared with previous work done in this area. We show that our design has a lower gate count than other designs that implement both the forward and the inverse mix columns operation.