Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Contemporary Logic Design
The Design of Rijndael
A Highly Regular and Scalable AES Hardware Architecture
IEEE Transactions on Computers
IEEE Transactions on Computers
A 10-Gbps full-AES crypto design with a twisted BDD S-box architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast exact minimization of BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The Advanced Encryption Standard (AES) has been widely used in many applications since adopted by the NIST in 2001. AES is often implemented in hardware for security purposes, but because of the complex nature of the algorithm, reliability is a major concern. The use of error-detecting codes (EDCs) and physical duplication are generally the two methods that have been used for fault detection, although EDCs are costly in run-time and duplication is costly in realestate. This paper proposes a method for making the S-box, which is by far the critical component of AES, totally self-checking using pseudo-nMOS technology. The fault detection method proposed in this paper has a lower latency than EDCs and requires less overhead than duplication. Although this method is shown only in constructing the S-box, the method can be scaled up to make the entire AES algorithm totally self-checking.