Self-checking and fault-tolerant digital design

Self-checking sequential circuits with self-healing ability

Proceedings of the 12th ACM Great Lakes symposium on VLSI

Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques

ACM Transactions on Embedded Computing Systems (TECS)

Logic Complement, a New Method of Checking the Combinational Circuits

Automation and Remote Control

Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures

Journal of Electronic Testing: Theory and Applications

Online and Offline BIST in IP-Core Design

IEEE Design & Test

Error-correction and crosstalk avoidance in DSM busses

Proceedings of the 2003 international workshop on System-level interconnect prediction

Model Checking the Design of an Unrestricted, Stuck-at Fault Tolerant, Asynchronous Sequential Circuit Using SMV

FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design

On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check

Journal of Electronic Testing: Theory and Applications

Error-correction and crosstalk avoidance in DSM busses

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A Technique for Designing Totally Self-Checking Domino Logic Circuits

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Improving quantum circuit dependability with reconfigurable quantum gate arrays

Proceedings of the 2nd conference on Computing frontiers

A Totally Self-Checking S-box Architecture for the Advanced Encryption Standard

ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design

Self-Stabilizing Microprocessor: Analyzing and Overcoming Soft Errors

IEEE Transactions on Computers

Analysis of the impact of bus implemented EDCs on on-chip SSN

Proceedings of the conference on Design, automation and test in Europe: Proceedings

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect

Robust codes and robust, fault-tolerant architectures of the Advanced Encryption Standard

Journal of Systems Architecture: the EUROMICRO Journal

Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic

Proceedings of the 17th ACM Great Lakes symposium on VLSI

Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems

Journal of Electronic Testing: Theory and Applications

Towards Nanoelectronics Processor Architectures

Journal of Electronic Testing: Theory and Applications

Interactive presentation: Improving the fault tolerance of nanometric PLA designs

Proceedings of the conference on Design, automation and test in Europe

Bilateral Testing of Nano-scale Fault-Tolerant Circuits

Journal of Electronic Testing: Theory and Applications

Towards fault tolerant parallel prefix adders in nanoelectronic systems

Proceedings of the conference on Design, automation and test in Europe

Self checking systolic FIFO stack

IMACS'08 Proceedings of the 7th WSEAS International Conference on Instrumentation, Measurement, Circuits and Systems

Estimating the latent time of fault detection in finite automaton tested in real time

Automation and Remote Control

Datapath error detection with no detection latency for high-performance microprocessors

WSEAS Transactions on Computers

Speed up Marouf and Friedman TSC berger codes checker

CSECS'08 Proceedings of the 7th conference on Circuits, systems, electronics, control and signal processing

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Constructing self-testing circuits with the use of step-by-step (cascade) control

Automation and Remote Control

On implementation of online testable state machines

ICC'09 Proceedings of the 13th WSEAS international conference on Circuits

New Self-Checking Booth Multipliers

International Journal of Applied Mathematics and Computer Science - Selected Problems of Computer Science and Control

Evolving and analysing "useful" redundant logic

ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware

On-line error detection and fast recover techniques for dependable embedded processors

On-line error detection and fast recover techniques for dependable embedded processors

One-to-Many: Context-Oriented Code for Concurrent Error Detection

Journal of Electronic Testing: Theory and Applications

An approach for implementing state machines with online testability

VLSI Design

System-level hardware-based protection of memories against soft-errors

Proceedings of the Conference on Design, Automation and Test in Europe

Efficient Concurrent Self-Test with Partially Specified Patterns

Journal of Electronic Testing: Theory and Applications

History index of correct computation for fault-tolerant nano-computing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Increasing fault-tolerance in cellular automata-based systems

UC'11 Proceedings of the 10th international conference on Unconventional computation

Note on reliability of a system complexity

Mathematical and Computer Modelling: An International Journal

Cellular automata-based systems with fault-tolerance

Natural Computing: an international journal

Inexact design: beyond fault-tolerance

Communications of the ACM

Circuit Level Concurrent Error Detection in FSMs

Journal of Electronic Testing: Theory and Applications

Preserving Hamming Distance in Arithmetic and Logical Operations

Journal of Electronic Testing: Theory and Applications