Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Advanced Fault Collapsing (Logic Circuits Testing)
IEEE Design & Test
Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis
Proceedings of the IEEE International Test Conference on Test and Design Validity
FedEx - a fast bridging fault extractor
Proceedings of the IEEE International Test Conference 2001
Fault Escapes in Duplex Systems
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A Scalable and Efficient Methodology to Extract Two Node Bridges from Large Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets
ITC '02 Proceedings of the 2002 IEEE International Test Conference
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Built-In Self-Test of Molecular Electronics-Based Nanofabrics
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Optimizing noise-immune nanoscale circuits using principles of Markov random fields
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
Test generation for combinational quantum cellular automata (QCA) circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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As the technology enters the nano dimension, the inherent unreliability of nanoelectronics is making fault-tolerant architectures increasingly necessary in building nano systems. Because fault-tolerant hardwares help to mask the effects caused by increased levels of defects, testing the functionality of the chip together with the embedded fault-tolerance becomes a tremendous challenge. In this paper, a new bilateral testing framework for nano circuits is proposed, where multiple stuck-at faults across different modules in a triple module redundancy (TMR) architecture are considered. In addition, a new test generator is presented for the bilateral testing that takes into account the enormous number of bilateral stuck-at faults possible with new types of guidance in the search, and it can generate a set of vectors that can test the TMR-based nano circuit as a single entity. Experimental results reported for ISCAS'85 and ITC99 circuits demonstrate that the bilateral testing can help to capture many more defects which the single stuck-at fault misses.