SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MACDAS: multi-level AND-OR circuit synthesis using two-variable function generators
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Technology adaption in logic synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
A case study in silicon compilation software engineering, HVDEV high voltage device layout generator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAGON: Technology binding and local optimization by DAG matching
25 years of DAC Papers on Twenty-five years of electronic design automation
Horizontal partitioning of PLA-based finite state machines
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Logic optimization algorithm by linear programming approach
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Timing optimization on mapped circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Behavioral Model Synthesis with Cones
IEEE Design & Test
Area and Timing Estimation for Lookup Table Based FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A new decomposition method for multilevel circuit design
EURO-DAC '91 Proceedings of the conference on European design automation
Bilateral Testing of Nano-scale Fault-Tolerant Circuits
Journal of Electronic Testing: Theory and Applications
iCOACH: A circuit optimization aid for CMOS high-performance circuits
Integration, the VLSI Journal
| Hi-index | 0.00 |
In order to compare logic synthesis and optimization systems, a set of benchmarks has been submitted to a number of authors. The results obtained are reported in the present proceedings. This short paper introduces the benchmarks as well as a set of criteria to measure the quality of logic synthesis systems.