Chortle: a technology mapping program for lookup table-based field programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Xmap: A technology mapper for table-lookup field-programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A tutorial on logic synthesis for lookup-table based FPGAs
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
On area/depth trade-off in LUT-based FPGA technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
100-hour design cycle: a test case
EURO-DAC '94 Proceedings of the conference on European design automation
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
EMPIRICAL EVALUATION OF MULTILEVEL LOGIC MINIMIZATION TOOLS FOR A FIELD-PROGRAMMABLE GATE ARRAY TECHNOLOGY
Technology mapping for a two-output RAM-based field programmable gate array
EURO-DAC '91 Proceedings of the conference on European design automation
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Layout-driven high level synthesis for FPGA based architectures
Proceedings of the conference on Design, automation and test in Europe
RTL Synthesis with Physical and Controller Information
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Layout-driven RTL binding techniques for high-level synthesis
ISSS '96 Proceedings of the 9th international symposium on System synthesis
An area estimation methodology for FPGA based designs at systemc-level
Proceedings of the 41st annual Design Automation Conference
Fast and accurate resource estimation of automatically generated custom DFT IP cores
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Optimization of the bias current network for accurate on-chip thermal monitoring
Proceedings of the Conference on Design, Automation and Test in Europe
Accurate Area, Time and Power Models for FPGA-Based Implementations
Journal of Signal Processing Systems
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The importance of efficient area and timing estimation techniques is well-established in High-Level Synthesis (HLS), since it allows more efficient exploration of the design space while providing HLS tools with the capability of predicting the effects of technology-specific tools on the design space. Much of previous work has focused on estimation techniques that use very simple cost models based solely on the gate and/or literal count. Those models are not accurate enough to allow effective design space exploration since the effects of interconnect can indeed dominate the final design cost. The situation becomes even worse when the design is targeted to Field Programmable Gate Array (FPGA) technologies since the wire delay may contribute up to 60% of the overall design delay. In this paper, we present an approach of estimating area and timing for lookup table based FPGAs that takes into account not only gate area and delay but also the wiring effects. We select Xilinx XC4000 series as our main concentration because of their popularity. We tested our estimator with several benchmarks and the results show that we can get accurate area and timing estimates efficiently.